`timescale 1ns/100ps

module ALU_7bit_tb();

wire [6:0]resultbus;
wire zerobit,overflowbit;


reg [6:0] Abus, Bbus;
reg ALUop0,ALUop1,ALUop2;

ALU_7bit_unsigned alu700(Abus, Bbus, resultbus, zerobit, overflowbit, ALUop0,ALUop1,ALUop2);

initial begin
Abus<=0001010; Bbus<=0000011; ALUop0<=0; ALUop1<=1; ALUop2<=0;
end

endmodule

